VIA Eden處理器列表

VIA Eden核心為VIA公司的第五代第六代微處理器產品,主要面向嵌入式市場

VIA Eden處理器列表

"Samuel 2" (150 nm)

型號頻率 (MHz)L2快取(KB)匯流排倍頻電壓功耗(W)腳座發行日代碼
Eden ESP 300300 MHz64 KiB66 MHz4.5×1.05 V2.5 WEBGADecember 11, 2001
Eden ESP 400400 MHz64 KiB100 MHz4×1.05 V3 WEBGADecember 11, 2001
Eden ESP 533533 MHz64 KiB133 MHz4×1.2 V5 WEBGADecember 11, 2001
Eden ESP 600600 MHz64 KiB133 MHz4.5×1.2 V6 WEBGADecember 11, 2001

"Nehemiah" (130 nm)

  • 指令集: MMX, SSE, VIA PadLock (AES, RNG)
型號頻率 (MHz)L2快取(KB)匯流排倍頻電壓功耗(W)CPU腳位發行日產品編號
Eden ESP7000733 MHz64 KiB133 MHz5.5×1.05 V6 WEBGAAugust 19, 2003
Eden ESP8000800 MHz64 KiB133 MHz6×1.05 V6 WEBGAFebruary 10, 2004
Eden ESP100001000 MHz64 KiB133 MHz7.5×1.05 V7 WEBGAFebruary 10, 2004
Eden ESP100001000 MHz64 KiB200 MHz5×1.05 V7 WEBGAFebruary 10, 2004

"Nehemiah" (130 nm)

型號頻率 (MHz)L2快取(KB)匯流排倍頻電壓功耗(W)腳座發行日代碼
Eden-N 533533 MHz64 KiB133 MHz4×0.9 V2.5/3.5 WNanoBGAOctober 14, 2003
Eden-N 800800 MHz64 KiB133 MHz6×0.95 V5 WNanoBGAOctober 14, 2003
Eden-N 1.0GHz1000 MHz64 KiB133 MHz7.5×1 V7 WNanoBGAOctober 14, 2003

"Esther" (標準電壓, 90 nm)

型號頻率 (MHz)L2緩存(KB)匯流排倍頻電壓功耗(W)腳座發行日代碼
Eden 400400 MHz128 KiB400 MT/s4×0.796 V2.5 WNanoBGA2January 17, 2006
Eden 500500 MHz128 KiB400 MT/s5×0.796 V3.5 WNanoBGA2January 17, 2006
Eden 600600 MHz128 KiB400 MT/s6×0.844 V5 WNanoBGA2January 17, 2006
Eden 800800 MHz128 KiB400 MT/s8×0.844 V5 WNanoBGA2January 17, 2006
Eden 1.0GHz1000 MHz128 KiB400 MT/s10×0.844 V5 WNanoBGA2January 17, 2006
Eden 1.2GHz1200 MHz128 KiB400 MT/s12×0.844-0.86 V7 WNanoBGA2January 17, 2006

"Esther" (超低電壓, 90 nm)

型號頻率L2快取前端匯流排倍頻核心電壓TDPIdle PowerCPU腳位發表時間產品編號
Eden ULV 500500 MHz128 KiB400 MT/s5×0.684 V1 W100 mWNanoBGA2August 23, 2007
Eden ULV 500500 MHz128 KiB400 MT/s5×0.6875 V1 W mWMobileBGA
Eden ULV 1.0 GHz1000 MHz128 KiB400 MT/s10×0.796 V3.5 W500 mWNanoBGA2January 17, 2006
Eden ULV 1.0 GHz1000 MHz128 KiB400 MT/s10×0.8000 V3.5 W mWMobileBGA
Eden ULV 1.5 GHz1500 MHz128 KiB400 MT/s15×0.956 V7.5 W500 mWNanoBGA2January 17, 2006
Eden ULV 1.6 GHz1600 MHz128 KiB800 MT/s7.5×≤0.988 V8 W mWNanoBGA2

"Eden X2" (40 nm)

型號頻率L2快取前端匯流排倍頻核心電壓TDPIdle PowerCPU腳位核心數發表時間
U4200E1 GHz64 KiB+64 KiB800 MT/s ?× ? V9 W ? mWFCBGA2March 1, 2011
U4100E800 MHz64 KiB+64 KiB533 MT/s ?× ? V5-6 W ? mWFCBGA2March 1, 2011

外部連結

另見

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